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E2U0037-28-82
Semiconductor MSM7602
Semiconductor Echo Canceler
This version: Aug. 1998 MSM7602 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7602 is an improved version of the MSM7520 with the same basic configuration. The MSM7602 uses a 19.2 MHz clock frequency to meet PHS, the 3 V power supply (2.7 V to 5.5 V), and compact packaging. Also, this device adds the howling detecter control pins and main clook output pins. (See the Appendix) The MSM7602 is a low-power CMOS IC device for canceling echo (in an acoustic system or telephone line) generated in a speech path. Echo is canceled, in digital signal processing, by estimating the echo path and generating a pseudo echo signal. When used as an acoustic echo canceler, the device cancels the acoustic echo between the loud speaker and the microphone which occurs during hands free communication such as with a cellular phone or a conference system phone. When used as a line echo canceler, the device cancels the line echo caused by impedance mismatching in a hybrid. In addition, the MSM7602 makes possible a quality conversation by controlling the noise level and preventing howling with howling detector, double talk detector, attenuation function, and a gain control function. The devise also controls the low level noise with a center clipping function. Further, the MSM7602 I/O interface supports m-law PCM . The use of a single chip CODEC, such as the MSM7566/7704 (3 V) or MSM7543/7533 (5 V), allows an economic and efficient echo canceler configuration.
FEATURES
* Handles both acoustic echoes and telephone line echoes. * Cancelable echo delay time: MSM7602-001 ................. For a single chip: 23 ms (max.) MSM7602-011 ................. For a cascade connection (can also be used for a single chip) Master chip: 23 ms (max.) Slave chip: 31 ms (max.) Cancelable up to 209 ms (1 master plus 6 slaves) For a single chip: 23 ms (max.) * Echo attenuation : 30 dB (typ.) * Clock frequency : 19.2 MHz External input and internal oscillator circuit are provided. * Power supply voltage : 2.7 V to 5.5 V * Package options: 28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : MSM7602-001GS-K) 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name : MSM7602-011GS-2K)
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Semiconductor
MSM7602
BLOCK DIAGRAM
MSM7602-001 (Single chip only)
RIN
S/P
Non-linear/ Linear
ATT
Gain
Linear/ Non-linear
P/S
ROUT
Howling Detector
Double Talk Detector
Power Calculator
Adaptive FIR Filter (AFF)
-
SOUT WDT PWDWN MCKO X1/CLKIN X2 SCKO SYNCO NLP HCL ADP ATT GC HD * Clock Generator Mode Selector P/S Linear/ Non-linear Center Clip ATT
+
+ Non-linear/
Linear
S/P
SIN RST VDD
I/O Controller VSS INT IRLD SCK SYNC
MSM7602-011 (Cascade connection or single chip)
RIN
S/P
Non-linear/ Linear
ATT
Gain
Howling Detector
Double Talk Detector
Power Calculator
SOUT WDT * PWDWN MCKO
P/S
Linear/ Non-linear
Center Clip
ATT
* Clock Generator
Mode Selector
X1/CLKIN X2 SCKO SYNCO NLP HCL ADP ATT GC MS HD INT IRLD SCK SYNC * * * * * If the MSM7602-011 is used in the slave mode, only the diagonally hatched blocks and the pins marked with * are used.
,
Linear/ Non-linear P/S ROUT Adaptive FIR Filter (AFF) Parallel I/O Port PD15 * PD 0 * OF1 * OF2 * SF1 * SF2 * SIN -
-
Parallel I/O Controller
+
+ Non-linear/
Linear
S/P
RST * VDD * VSS *
I/O Controller
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Semiconductor
MSM7602
PIN CONFIGURATION (TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin Plastic SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Pin 1 2 3 4 5 6 7
Symbol NLP HCL ADP VDD ATT INT IRLD
Pin 8 9 10 11 12 13 14
Symbol SIN RIN SCK SYNC SOUT ROUT VSS
Pin 15 16 17 18 19 20 21
Symbol VSS HD X1/CLKIN X2 VDD PWDWN VSS
Pin 22 23 24 25 26 27 28
Symbol SYNCO SCKO RST WDT GC VDD MCKO
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Semiconductor
MSM7602
56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin Plastic QFP 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Symbol NLP HCL ADP MS ATT INT IRLD SIN RIN SCK SYNC SOUT ROUT VSS
Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Symbol PD0 PD1 PD2 PD3 PD4 PD5 VSS PD6 PD7 PD8 PD9 PD10 PD11 HD
Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Symbol PD12 PD13 X1/CLKIN X2 VDD PWDWN VSS SYNCO SCKO RST WDT GC VDD VDD
Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Symbol * PD14 PD15 MCKO SF2 OF1 VSS * VSS SF1 OF2 VDD VDD *
*: No connect pin
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Semiconductor
MSM7602
PIN DESCRIPTIONS (1/5)
Pin 28-pin 56-pin SSOP 1 QFP 1 NLP I Control pin for the center clipping function. This pin forces the SOUT output to a minimum value when the SOUT signal is below -54 dBm0. Effective for reducing low-level noise. * Single Chip or Master Chip in a Cascade Connection "H": Center clip ON "L": Center clip OFF * Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. Through mode control. When this pin is in the through mode, RIN and SIN data is output to ROUT and SOUT. At the same time, the coefficient of the adaptive FIR filter is cleared. * Single Chip or Master Chip in a Cascade Connection "H": Through mode "L": Normal mode (echo canceler operates) * Slave Chip in a Cascade Connection Same as master This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. AFF coefficient control. This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. This pin is used when holding the AFF coefficient which has been once converged. * Single Chip or Master Chip in a Cascade Connection "H": Coefficient fix mode "L": Normal mode (coefficient update) * Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. Select signal. This pin selects between the master chip and slave chip when used in a cascade connection. "L": Single chip or master chip "H": Slave chip Symbol Type Description
2
2
HCL
I
3
3
ADP
I
--
4
MS
I
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Semiconductor (2/5)
Pin 28-pin 56-pin SSOP 5 QFP 5 ATT I Symbol Type Description
MSM7602
Control for the ATT function. This pin prevents howling by attenuators (ATT) for the RIN input and SOUT output. If there is input only to RIN, the ATT for the SOUT output is activated. If there is no input to SIN, or if there is input to both SIN and RIN, the ATT for the RIN input is activated. Either the ATT for the RIN output or the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is 6 dB. * Single Chip or Master Chip in a Cascade Connection "H": ATT OFF "L": ATT ON "L" is recommended if performing echo cancellation. * Slave Chip in a Cascade Connection Fixed at "L" This input signal is loaded in synchronization with the falling edge of the INT signal or the rising edge of the RST signal. Interrupt signal which starts 1 cycle (8 kHz) of the signal processing. Signal processing starts when "H"-to-"L" transition is detected. * Single Chip or Master Chip in a Cascade Connection Connect the IRLD pin. * Slave Chip in a Cascade Connection Connect the IRLD pin of the master chip. INT input is invalid for 100 ms after reset due to initialization. Refer to the control pin connection example. Load detection signal output when the SIN and RIN serial input data is loaded in the internal registers. * Single Chip Connect to the INT pin. * Master Chip in a Cascade Connection Connect to the INT pin of the master chip and all the slave chips. * Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example. Transmit serial data. Input the PCM signal synchronized to SYNC and SCK. Data is read in at the falling edge of SCK. Receive serial data. Input the PCM signal synchronized to SYNC and SCK. Data is read at the falling edge of SCK. Clock input for transmit/receive serial data. This pin uses the external SCK or the SCKO. Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).
6
6
INT
I
7
7
IRLD
O
8
8
SIN
I
9
9
RIN
I
10
10
SCK
I
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Semiconductor (3/5)
Pin 28-pin 56-pin SSOP 11 QFP 11 SYNC I Sync signal for transmit/receive serial data. This pin uses the external SYNC or SYNCO. Input the PCM CODEC transmit/receive sync signal (8 kHz). Transmit serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state during no data output. Receive serial data. Outputs the PCM signal synchronized to SYNC and SCK. This pin is in a high impedance state during no data output. Symbol Type Description
MSM7602
12
12
SOUT
O
13
13
ROUT
O
-- -- -- -- -- -- -- -- 16
15
PD0
I/O
20 22
PD5 PD6
This is the bidirectional bus pin for parallel data transfer between the master chip and slave chip when used in a cascade connection. The PD15 pin corresponds to MSB. This pin is in a high impedance state during no data output. Data is loaded in at the falling edge of SFx.
-- --
27 29 30 44 45 28 17 31 18 32
PD11 PD12 PD13 PD14 PD15 HD I Controls the howling detect function. This pin detets and cancels a howling generated during hand-free talking for acoustic system. This function is used to cancel acoustic echoes. * Single Chip or Master Chip in a Cascade Connection "L": Howling detector ON "H": Howling detector OFF * Slave Chip in a Cascade Connection Fixed at "L" External input for the basic clock (17.5 to 20 MHz) or for the crystal oscillator. When the internal sync signal (SYNCO, SCKO) is used, input the basic clock of 19.2 MHz. Crystal oscillator output. Used to configure the oscilation circuit. Refer to the internal clock generator circuit example. When inputting the basic clock externally, insert a 5 pF capacitor with excellent high frequency characteristics between X2 and GND.
X1/CLKIN
X2
-- --
I O
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Semiconductor (4/5)
Pin 28-pin 56-pin SSOP 20 QFP 34 PWDWN I Symbol Type Description
MSM7602
Power-down mode control when powered down. "L": Power-down mode "H": Normal operation mode During power-down mode, all input pins are disabled and output pins are in the following states : High impedance : SOUT, ROUT, PD0 to 15 "L": SYNCO, SCKO, MCKO "H": OF1, OF2, X2 Holds the last state : WDT, IRLD Reset after the power-down mode is released. 8 kHz sync signal for the PCM CODEC. Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin. Leave it open if using an external SYNC. Transmit clock signal (256 kHz) for the PCM CODEC. Connect to the SCK pin and the PCM CODEC transmit/receive clock pin. Leave it open if using an external SCK. Reset signal. "L": Reset mode "H": Normal operation mode Due to initialization, input signals are disabled for 100 ms after reset (after RST is returned from L to H). Input the basic clock during the reset. Output pins during the reset are in the following states : High impedance: SOUT, ROUT, PD0 to 15 "L": WDT "H": OF1, OF2 Not affected: X2, SYNCO, SCKO, IRLD, MCKO Test program end signal. This signal is output when the one cycle (8kHz) of processing is completed. Leave it open. Input signal by which the gain controller for the RIN input is controlled and the RIN input level is controlled and howling is prevented. The gain controller adjusts the RIN input level when it is -20 dBm0 or above. RIN input levels from -20 to -11.5 dBm0 will be suppressed to -20 dBm0 in the attenuation range from 0 to 8.5 dB. RIN input levels above -11.5 dBm0 will always be attenuated by 8.5 dB. * Single Chip or Master Chip in a Cascade Connection "H": Gain control ON "L": Gain control OFF "H" is recommended for echo cancellation. * Slave Chip in a Cascade Connection Fixed at "L" This pin is loaded in synchronization with the falling edge of the INT signal or the rising edge of RST.
22
36
SYNCO
O
23
37
SCKO
O
24
38
RST
I
25
39
WDT
O
26
40
GC
I
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Semiconductor (5/5)
Pin 28-pin 56-pin SSOP 28 -- QFP 46 47 MCKO SF2 O I Symbol Type Description
MSM7602
Basic clock (19.2 MHz). Parallel data transfer flag. * Single Chip Fixed at "H" * Master Chip in a Cascade Connection Fixed at "H" * Slave Chip in a Cascade Connection Connect OF2 of the master chip to the 1st stage slave chip. Connect OF1 of the previous stage slave chip to the 2nd and later stage slave chips. Refer to the control pin connection example. Parallel data transfer flag. * Single Chip Leave open. * Master Chip in a Cascade Connection Connect to the SF1 of all slaves. * Slave chip in a Cascade Connection Connect to the SF2 of the next stage slave chip. Connect the last stage slave chip to the SF1 of the master chip. Refer to the control pin connection example. Parallel data transfer flag. * Single Chip Connect OF2. * Master Chip in a Cascade Connection Connect OF1 of the last stage slave chip. * Slave Chip in a Cascade Connection Connect OF1 of master chip for all slave chips. Refer to the control pin connection example. Parallel data output flag. * Single Chip Connect to SF1. * Master Chip in a Cascade Connection Connect to SF2 of the 1st stage slave chip. * Slave Chip in a Cascade Connection Leave open. Refer to the control pin connection example.
--
48
OF1
O
--
52
SF1
I
--
53
OF2
O
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Semiconductor
MSM7602
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG -- Ta = 25C Condition Rating -0.3 to +7 -0.3 to VDD + 0.3 1 -55 to +150 Unit V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage High Level Input Voltage Low Level Input Voltage Operating Temperature Symbol VDD VSS VIH VIL Ta X1 pin -- -- Condition -- -- Pins other than X1 Min. 2.7 -- 2.0 2.2 0 -40
(VDD = 2.7 V to 3.6 V) Typ. 3.3 0 -- -- -- +25 Max. 3.6 -- VDD VDD 0.5 +85 Unit V V V V V C
(VDD = 4.5 V to 5.5 V) Parameter Power Supply Voltage Power Supply Voltage High Level Input Voltage Low Level Input Voltage Operating Temperature Symbol VDD VSS VIH VIL Ta X1, SCK pins -- -- Condition -- -- Pins other than X1, SCK Min. 4.5 -- 2.4 3.5 0 -40 Typ. 5 0 -- -- -- +25 Max. 5.5 -- VDD VDD 0.8 +85 Unit V V V V V C
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Output Leakage Current Symbol VOH VOL IIH IIL IOZH Condition IOH = 40 mA IOL = 1.6 mA VIH = VDD MS with pull-down VIL = VSS SF1, SF2 with pull-up VOH = VDD PD15 to PD0 Low Level Output Leakage Current IOZL VOL = VSS with pull-up
Input other than the above
(VDD = 2.7 V to 3.6 V, Ta = -40C to +85C) Min. 2.2 0 -- 6 -1 -60 -- -60 -1 -- -- -- -- Typ. -- -- 0.1 60 -0.1 -33 0.1 -33 -0.1 20 10 -- -- Max. VDD 0.4 1 120 -- -6 1 -6 -- 30 50 15 20 Unit V V mA mA mA mA mA mA mA mA mA pF pF
Power Supply Current (Operating) Power Supply Current (Stand-by) Input Capacitance Output Load Capacitance
IDDO IDDS CI CLOAD
-- PWDWN = "L" -- --
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Semiconductor
MSM7602
Parameter High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Output Leakage Current
Symbol VOH VOL IIH IIL IOZH
Condition IOH = 40 mA IOL = 1.6 mA VIH = VDD MS with pull-down VIL = VSS SF1, SF2 with pull-up VOH = VDD
(VDD = 4.5 V to 5.5 V, Ta = -40C to +85C) Typ. Min. Max. Unit 4.2 0 -- 10 -10 -100 -- -- -- 0.1 100 -0.1 -50 0.1 -50 -0.1 30 10 -- -- VDD 0.4 10 200 -- -10 10 -10 -- 45 50 15 20 V V mA mA mA mA mA mA mA mA mA pF pF
PD15 to PD0 Low Level Output Leakage Current IOZL VOL = VSS with pull-up
Input other than the above
-100 -10 -- -- -- --
Power Supply Current (Operating) Input Capacitance Input Capacitance Output Load Capacitance
IDDO IDDS CI CLOAD
-- PWDWN = "L" -- --
Echo Canceler Characteristics (Refer to Characteristics Diagram)
Parameter Symbol Condition RIN = -10 dBm0 (5 kHz band white noise) Echo Attenuation LRES E. R. L. (echo return loss) = 6 dB TD = 20 ms ATT, GC, NLP: OFF Cancelable Echo Delay Time for a Single Chip or a Master Chip in a Cascade Cancelable Echo Delay Time for a Slave Chip in a Cascade TDS TD RIN = -10 dBm0 (5 kHz band white noise) E. R. L. = 6 dB ATT, GC, NLP: OFF -- -- 31 ms -- -- 23 ms -- 30 -- dB Min. Typ. Max. Unit
11/29
Semiconductor AC Characteristics
MSM7602
(Ta = -40C to +85C) Parameter Clock Frequency When Internal Sync Signal is not used Clock Cycle Time When Internal Sync Signal is not used Clock Duty Ratio Clock "H" Level Pulse Width fc = 19.2 MHz Clock "L" Level Pulse Width fc = 19.2 MHz Clock Rise Time Clock Fall Time Sync Clock Output Time Internal Sync Clock Frequency Internal Sync Clock Output Cycle Time Internal Sync Clock Duty Ratio Internal Sync Signal Output Delay Time Internal Sync Signal Period Internal Sync Signal Output Width Transmit/receive Operation Clock Frequency Transmit/receive Sync Clock Cycle Time Transmit/receive Sync Clock Duty Ratio Transmit/receive Sync Signal Period Sync Timing Sync Signal Width Receive Signal Setup Time Receive Signal Hold Time Receive Data Input Time IRLD Signal Output Delay Time IRLD Signal Output Width Serial Output Delay Time Reset Signal Input Width Reset Start Time Reset End Time Processing Operation Start Time Symbol fC tMCK tDMC tMCH tMCL tr tf tDCM fCO tCO tDCO tDCC tCYO tWSO fSCK tSCK tDSC tCYC tXS tSX tWSY tDS tDH tID tDIC tWIR tSD tXD tWR tDRS tDRE tDIT VDD = 2.7 V to 3.6 V Min. -- 17.5 -- 50 40 20.8 20.8 -- -- -- -- -- -- -- -- -- 64 0.488 40 123 45 45 tSCK 45 45 -- -- -- -- -- 1 5 -- 100 Typ. 19.2 -- 52.08 -- -- -- -- -- -- -- 256 3.9 50 -- 125 tCO -- -- 50 125 -- -- -- -- -- 7tSCK -- tSCK -- -- -- -- -- -- Max. -- 20 -- 57.14 60 31.3 31.3 5 5 30 -- -- -- 5 -- -- 2048 15.6 60 -- -- tCYC-tSCK -- -- -- -- 138 -- 90 90 -- -- 52 -- VDD = 4.5 V to 5.5 V Min. -- 17.5 -- 50 40 20.8 20.8 -- -- -- -- -- -- -- -- -- 64 0.488 40 123 45 45 tSCK 45 45 -- -- -- -- -- 1 5 -- 100 Typ. 19.2 -- 52.08 -- -- -- -- -- -- -- 256 3.9 50 -- 125 tCO -- -- 50 125 -- -- -- -- -- 7tSCK -- tSCK -- -- -- -- -- -- Max. -- 20 -- 57.14 60 31.3 31.3 5 5 30 -- -- -- 5 -- -- 2048 15.6 60 -- -- tCYC-tSCK -- -- -- -- 138 -- 90 90 -- -- 52 -- Unit MHz ns ns ns ns ns ns ns kHz ms % ns ms ms kHz ms % ms ns ns ms ns ns ms ns ms ns ns ms ns ns ms
12/29
Semiconductor AC Characteristics (Continued)
MSM7602
(Ta = -40C to +85C) Parameter Power Down Start Time Power Down End Time Control Pin Setup Time (INT) Control Pin Hold Time (INT) Control Pin Setup Time (RST) Control Pin Hold Time (RST) Parallel Data Output Signal Width Flag Signal Output Time Flag Signal Output Width Flag Signal Input Width Data Read Setup Time Data Read Hold Time Symbol tDPS tDPE tDTS tDTH tDSR tDHR tWPD tDF tWFO tWFI tFS fFH VDD = 2.7 V to 3.6 V Min. -- -- 20 120 20 10 -- -- -- -- -- -- Typ. -- -- -- -- -- -- 2tMCK tMCK tMCK/2 tWFO 20 10 Max. 111 15 -- -- -- -- -- -- -- -- -- -- VDD = 4.5 V to 5.5 V Min. -- -- 20 120 20 10 -- -- -- -- -- -- Typ. -- -- -- -- -- -- 2tMCK tMCK tMCK/2 tWFO 20 10 Max. 111 15 -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
13/29
Semiconductor
MSM7602
TIMING DIAGRAM
Clock Timing
fC, tMCK, tDMC X1/CLKIN tDCM SCKO fCO, tCO SCKO tDCC tDCC tCYO SYNCO tWSO tDCO tDCM tMCH tMCL tr tf
Serial Input Timing
fSCK, tSCK SCK tXS tSX tCYC tDSC
SYNC tWSY tDS SIN RIN MSB 7 tDH LSB 0 tDIC IRLD tWIR tDIC MSB 7
6
5
4 tID
3
2
1
14/29
Semiconductor Serial Output Timing
MSM7602
fSCK, tSCK SCK tXS tSX tCYC
tDSC
SYNC
SOUT ROUT
Operation Timing After Reset
tWR
RST
Internal operaion
Power Down Timing
PWDWN
Internal Operation
,
tSD tXD tWSY tXD High-Z MSB 7 6 5 4 3 2
tXD LSB High-Z 0 MSB 7
1
*Reset timing can be asynchronous tDIT
tDRS
tDRE
Reset
Initialization
Processing Start
Note: INT is invalid in the diagonally shaded interval.
tDPS
tDPE Processing Start
Power Down
15/29
Semiconductor Control Pin Load-in Timing
*tCYC INT(IRLD) tDTS NLP, HCL, HD, ATT, ADP, GC tWR RST tDSR NLP, HCL, HD, ATT, ADP, GC tDHR tDTH
MSM7602
*For IRLD output timing, refer to Serial Input Timing
Parallel Output Timing
tWPD PD15 PD 0 tDF OF1 OF2 tWFO High-Z Output Data High-Z
Parallel Input Timing
tWFI SF1 SF2 tFS PD15 PD 0 tFH Input Data
-
-
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Semiconductor
MSM7602
HOW TO USE THE MSM7602
The MSM7602 cancels (based on the RIN signal) the echo which returns to SIN. Connect the base signal to the R side and the echo generated signal to the S side. Connection Methods According to Echos Example 1: Canceling acoustic echo (to handle acoustic echo from line input)
MSM7602 ROUT Acoustic echo CODEC SIN AFF RIN CODEC SOUT H Line input
+
- +
Example 2:
Canceling line echo (to handle line echo from microphone input)
MSM7602 RIN CODEC SOUT AFF ROUT CODEC H Line echo
Microphone input
- +
+
SIN
Example 3:
Canceling line echo in a cascade connection (to handle line echo from microphone input)
RIN CODEC SOUT MSM7602 ROUT Master AFF CODEC H H
Microphone input
-
+
+
SIN Line echo PD0 - 15
Slave AFF
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Semiconductor
MSM7602
Example 4: Canceling of both acoustic echo and line echo (to handle both acoustic echo from line input and line echo from microphone input)
MSM7602 ROUT Acoustic echo CODEC SIN AFF RIN SOUT
MSM7602 SIN
Line input
+
- +
SOUT
RIN
AFF
Microphone input
For acoustic echo
For line echo
Control Pin Connection Example Single chip connection
NLP HCL ADP ATT GC HD PWDWN RST MS * * PD15 NLP * PD 0 HCL ADP ATT GC HD PWDWN RST INT IRLD SF1 * * OF1 SF2 * * OF2
+5 V
Asterisk (*) indicates a pin only for the MSM7602-011
2-stage cascade connection Master + (slave 1)
Master chip MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2
-
+5 V
NLP HCL ADP ATT GC HD PWDWN RST
+5 V
Slave chip MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2
-
+
CODEC ROUT Line echo H
+ -
-
18/29
Semiconductor 4-stage cascade connection Master + (slave 3)
MSM7602
NLP HCL ADP ATT GC HD PWDWN RST
+5 V
Master chip MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 -
+5 V
Slave chip 1 MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 -
+5 V
Slave chip 2 MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 -
+5 V
Slave chip 3 MS PD15 NLP HCL PD 0 ADP ATT GC HD PWDWN RST INT IRLD OF1 SF1 OF2 SF2 -
Internal Clock Generator Circuit Example
MSM7602 X1/CLKIN R X2 XTAL : 19.2 MHz R : 1 MW C1 : 27 pF C2 : 27 pF C2 GND
C1 GND
XTAL
External Clock Input Circuit Example
MSM7602 X1/CLKIN X2
CLK
5pF
GND
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Semiconductor
MSM7602
ECHO CANCELER CHARACTERISTICS DIAGRAM
ERL vs. echo attenuation 40 30 20 10 0 40 30 20 10 0 RIN input level vs. echo attenuation
Echo attenuation [dB]
40
30
20
10
0
-10
Echo attenuation [dB]
-50 -40 -30 -20 -10 RIN input level [dBm] 0 dBm = 2.2 dBm0 Measurement Conditions RIN input: 5 kHz band white noise Echo delay time TD = 20 ms ERL = 6 dB ATT, GC, NLP = OFF Power supply voltage 5 V
0
ERL [dB] Measurement Conditions RIN input = -10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) Echo delay time TD = 20 ms ATT, GC, NLP = OFF Power supply voltage 5 V Echo delay time vs. echo attenuation 30
Echo attenuation [dB]
Measurement Conditions RIN input = -10 dBm 5 kHz band white noise (0 dBm = 2.2 dBm0) ERL = 6 dB ATT, GC, NLP = OFF The second through seventh chips are connected in a cascade. Power supply voltage 5 V
20 10 0 0 1 50 2 3 100 4 150 5 6 200 7chip
Echo delay time [ms]
Note:
The characteristics above are for the MSM7543 (VDD 5 V, m-law interface). The MSM7566 (VDD 3 V, m-law interface) provides the same characleristics without input and output levels. Refer to are PCM CODEC data sheet. MSM7543 (for both transmit and receive) 0 dBm0 = 0.6007 Vrms = -2.2 dBm (600 W) MSM7566 (for transmit side) 0 dBm0 = 0.35 Vrms = -6.9 dBm (600 W) (for receive side) 0 dBm0 = 0.5 Vrms = -3.8 dBm (600 W)
20/29
Semiconductor Measurement System Block Diagram
White noise generator L. P. F. RIN 5 kHz MSM7543 A PCM m-law CODEC Level meter SOUT A PCM RIN ROUT MSM7543 PCM A
MSM7602
TD Delay Echo delay time ATT ERL (echo return loss)
MSM7602 SOUT SIN
m-law CODEC PCM A
Power supply voltage 5 V
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Semiconductor
MSM7602
APPLICATION CIRCUIT
Bidirectional Connection Example
Use the MSM7704-01GS-VK for PCM CODEC when VDD 3V. The MSM7533 and MSM7704 are pin compatible. 2ch CODEC MSM7533VGS-K R2 DV R3 21 AIN1 22 GSX1 4 AOUT1 13 12 15 10 16 19 5 6 DOUT1 DIN1 XSYNC RSYNC BCLK A/m PDN CHP 24 AIN2 GSX2 23 2 AOUT2 14 DOUT2 DIN2 11 8 VDD 1 SGC AG 18 C9 + C10 C11 (AG) AV R6 R7 DV
Microphone input
C1
R1
R5
C5 Line input Line output
Speaker output
DV
DG 9
DV R4
For cancellation of acoustic echo MSM7602-001GS-K 8 SIN 13 ROUT 11 10 22 23 6 7 20 24 28 DV SYNC SCK SYNCO SCKO INT IRLD PWDWN RST MCKO 12 SOUT 9 RIN NLP HCL ADP ATT GC HD WDT X1 1 2 3 5 26 16 25 17 R9 18 X2 VSS 14 VSS 15 VSS 21
DV R10
DV R11
For cancellation of line echo MSM7602-001GS-K 12 SOUT 9 RIN 8 SIN 13 ROUT SYNC SCK SYNCO SCKO INT IRLD PWDWN RST 11 10 22 23 6 7 20 24 28 DV
DV R8
DV
DV
PWDWN RST
C12 C13 X1
1 2 3 5 26 16 25
NLP HCL ADP ATT GC HD WDT X1 X2 VSS VSS VSS C6 C7
4 VDD 19 V DD 27 V DD + C2 C3
17 C14 18 14 15 21
4 VDD VDD 19 VDD 27 +
R1 = 20 kW R2 = 20 kW R3 = 2.2 kW R4 = 10 kW R10 = 10 kW
C1 = 1 mF C2 = 10 mF C3 = 0.1 mF C4 = 0.1 mF
R5 = 20 kW R6 = 20 kW R7 = 2.2 kW R8 = 10 kW R11 = 10 kW
C5 = 1 mF C6 = 10 mF C7 = 0.1 mF C8 = 0.1 mF
C9 = 0.1 mF C10 = 10 mF C11 = 0.1 mF
R9 = 1 MW C12 = 27 pF C13 = 27 pF X1 = 19.2 MHz C14 = 5 pF
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R9 R10 R5 Master
PCMOUT PCMIN BCLOCK RSYNC XSYNC SG AIN VFRO AIN+
MSM7543GS-VK R4 Slave MSM7543GS-VK C5 RIN SOUT
SIN
C1 23 6 GSX 21 22 1 R8 R7 R6
PCMOUT
ROUT
PCMIN
23 AIN + 6 VFRO 21 GSX
BCLOCK
R2
RSYNC
8 SIN 13 ROUT 10 SCK 11 SYNC
8 SIN 13 ROUT 10 SCK 11 SYNC
Semiconductor
R1 38 RST 34 PWDWN 10 PDM 19 TMC 3 AOUT- 5 PWI
SGC
22 AIN- 38 RST 34 PWDWN
XSYNC
13 12 15 11 14
13 12 15 11 14
R3
Cascade Connection Example
1 SG 3 AOUT- 5 24
VDD 8
PDM
10
PWI
24
TMC 19
SGC
R12 C3
+
8V DD
C7 R13
AG
C2
C9
16
AG
MSM7602-011GS-2K
MSM7602-011GS-2K
DG
9
16
C10
+
9 DG
C6
When VDD is 3 V, use the MSM7566 for PCM CODEC. The MSM7543 and MSM7566 are pin compatible.
C11
X1
NLP HCL ADP MS ATT GC HD SCKO SYNCO X1 C13 + C8
NLP HCL ADP MS ATT GC HD SCKO SYNCO X1
1 2 3 4 5 40 28 37 36 31
C12
C4
+
1 2 3 4 5 40 28 37 36 31 R11 32 33 41 42 55 54 51 14 21 X2 VDD VDD VDD VDD VDD VSS VSS VSS 46 MCKO 39 WDT 35 VSS 49 VSS 56-Pin QFP 46 MCKO 39 WDT 35 VSS 49 VSS 56-Pin QFP X2 VDD VDD VDD VDD VDD VSS VSS VSS 32 33 41 42 55 54 51 14 21
SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD R1 > 50 kW R2 > 20 kW R3 > 20 kW R4 = 2.2 kW R5 = 10 kW R6 > 50 kW C1 = 0.1 mF C2 = 10 mF C3 = 0.1 mF C4 = 10 mF C5 = 0.1 mF R7 > 20 kW R8 > 20 kW R9 = 2.2 kW R10 = 10 kW R12 = 0-22 W R13 = 0-22 W C6 = 10 mF C7 = 0.1 mF C8 = 10 mF C9 = 0.1 mF C10 = 0.1 mF
12 9 45 44 30 29 27 26 25 24 23 22 20 19 18 17 16 15 53 47 48 52 6 7 SOUT RIN PD15 PD14 PD13 PD12 PD11 PD10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 OF2 SF2 OF1 SF1 INT IRLD
12 9 45 44 30 29 27 26 25 24 23 22 20 19 18 17 16 15 53 47 48 52 6 7
MSM7602
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RST PWDWN
R11 = 1 MW C13 = 5 pF C11 = 27 pF C12 = 27 pF X1 = 19.2 MHz
Semiconductor
MSM7602
NOTES ON USE
1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be amplified, the echo can not be eliminated. Refer to the characteristics diagram for ERL vs. echo attenuation quantity. 2. Set the level of the analog input so that the PCM CODEC does not overflow. 3. The recommended input level is -10 to -20 dBm0. Refer to the characteristics diagram for the RIN input level vs. echo attenuation quantity. 4. Applying the tone signal to this echo canceler for long duration may decrease echo attenuation. When used with the HD pin "L" (howling detector ON), this echo canceler may operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher level than the signal being input to RIN is input to the SIN pin. A signal should therefore be input either to the RIN pin or to the SIN pin. If, however, the tone signal is input to the SIN pin while a signal is input to the RIN pin, the ADP, HD, or HCL pin must be set to "H". 5. For changes in the echo path (retransmit, circuit switching during transmission, and so on), convergence may be difficult. Perform a reset, to make it converge. If the state of the echo path changes after a reset, convergence may again be difficult. In cases such as a change in the echo path, perform a reset each time. 6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock simultaneously with power ON. If powering down immediately after power ON, be sure fast input 10 or more clocks of the basic clock. 7. After powering ON, be sure to reset. 8. After the power down mode is released (when the PWDWN pin is changed to "H" from "L"), be sure to reset the device. 9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less than 30 dB.
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Semiconductor
MSM7602
EXPLANATION OF TERMS
This function prevents howling and controls the noise level with the attenuator for the RIN input and SOUT output. Refer to the explanation of pins (ATT pin). Echo Attenuation : If there is talking (input only to RIN) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (canceled amount) when the echo canceler is not used and when it is used. Echo attenuation = (SOUT level during through mode operation) - (SOUT level during echo canceler operation) [dB] Echo Delay Time : This is the time from when the signal is output from ROUT until it returns to SIN as an echo. Acoustic Echo : When using a hands free phone, and so on, the signal output from the speaker echoes and is input again to the microphone. The return signal is referred to as acoustic echo. Telephone Line Echo : This is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. Gain Control Function : This function prevents howling and controls the sound level with a gain controller for the RIN input. Refer to the explanation of pins (GC pin). Center Clipping Function : This function forces the SOUT output to a minimum value when the signal is below -57 dBm0. Refer to the explanation of pins (NLP pin). Double Talk Detection : Double talk refers to a state in which the SIN and RIN signals are input simultaneously. In a double talk state, a signal outside the echo signal which is to be canceled can be input to the SIN input, resulting in misoperation. The double talk detector prevents such misoperation of the canceler. Howling Detection : This is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands free talking. Howling not only interferes with talking, but can also cause in misoperation of the echo canceler. The howling detector prevents such misoperation and prevents howling. Echo Return Loss (ERL) : When the signal output from ROUT returns to SIN as an echo, ERL refers to how much loss there is in the signal level during ROUT. ERL = (ROUT level) - (SIN level of the ROUT signal which returns as an echo) [dB] If ERL is positive (ROUT > SIN), the system is an attenuator system. If ERL is negative (ROUT < SIN), the system is an amplifier system. PHS : Personal Handy Phone System. Attenuating Function :
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Semiconductor
MSM7602
APPENDIX
Differences Between the MSM7602 and the MSM7520/7620
Introduction The MSM7602 is the improved version of the MSM7520 with improved usage. Thus, there are no differences in echo canceling characteristics. Enhancements * A new clock frequency of 19.2 MHz. The basic clock frequency of the MSM7520/7620 was 18 or 38 MHz, while the basic clock frequency of MSM7602 is 19.2 MHz. (MSM7602 can be applied at a frequency of 18 MHz. However, external SYNC and SCK are required because the periods of SYNCO and SCKO are varied.) * Adoption of full-fledged 8-bit data through-mode In the through-mode for the MSM7520 (HCL pin: "H"), an internally processed PCM signal was used. Therefore, only the negative minimum value (7FHEX) was converted into the corresponding positive minimum value (FFHEX). Analog to analog conversion causes no problem since both values are the minimum ones, but data transfer in the through-mode encounters problems. Hence, in the MSM7620/7602, the complete data trough-mode has been implemented. * Control of input timing to control pins (NLP, HCL, ADP, ATT and GC) In MSM7520, asynchronous changes in a control pin may result in malfunctioning. This problem stems from the fact that information on control pins is checked several times during the execution of a program over one cycle and the state of a control pin is changed between the first and second half periods. The MSM7620/7602 provides an internal circuit for using an INT signal to hold control pin information for one cycle. Thus, external timing control is not needed. The howling detector control pin (HD) is added. The MSM7602 can prevent the false detection of the howling detecter cause by tone signals by providing the howling detecter control pins. * Introduction of 256 kHz internal clock output (SCKO) for PCM transmission Internal sync signals (SYNCO and SCKO) in MSM7520/7620 are rated at 8 kHz and 200 kHz, respectively. At a frequency of 8 kHz, PCM multiplexing can be applied to no more than three channels. In the MSM7602, SCKO is rated at 256 kHz, while SYNCO at 8 kHz. Thus, PCM multiplexing can be applied with up to four channels. * Addition of basic clock output The use of a crystal oscillator for a clock in the MSM7520/7620 requires an oscillating circuit installed in each of two or more cascade-connected IC chips. Since the MSM7602 supports basic clock output, only one IC chip requires an oscillating circuit. (The MSM7602-001TS-K does not provide the basic clock output.)
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Semiconductor * Small-sized package MSM7602 MSM7602-001GS-K :28-pin SSOP MSM7602-011GS-2K :56-pin QFP MSM7520 : 14.0 14.0 3.75 mm MSM7620 : 14.0 14.0 2.1 mm * Supply voltage rated at 3 volts MSM7520/7620 4.5 V to 5.5 V MSM7602 2.7 V to 5.5 V
MSM7602
Package code Package size (mm) :SSOP28-P-485-0.65-K :9.5 10.5 1.85 :QFP56-P-910-0.65-2K :9.5 10.5 1.85
5 V typ. 3.3 V or 5 V typ.
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Semiconductor
MSM7602
PACKAGE DIMENSIONS
(Unit : mm)
SSOP28-P-485-0.65-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.39 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM7602
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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